This invention relates to a semiconductor memory device having the memory cells comprised of transistors and capacitors. More particularly, it relates to a semiconductor memory device prepared by using high dielectric film or ferroelectric film for the capacitor insulator film of the device.
Known dynamic random access memories (DRAMs) having the memory cells comprised of transistors and capacitors of the type under consideration have paved the way to a higher degree of integration mainly by down-sizing through micronization. However, as the trend of micronization goes on, the surface area available to capacitors is reduced and, nowadays, capacitors are arranged three-dimensionally in a memory device and the lateral sides of the device are used to secure the capacity required for storing data. The process of manufacturing three-dimensionally arranged capacitors such as those referred to as trench type or stack type is a long and tedious one and consequently involves high manufacturing cost. It is a serious concern of the industry that capacitors as small as 0.1 .mu.m, if produced in the near future and arranged three-dimensionally, may not be able to secure the storage capacity required for the memory cells comprising them.
In line with the problem of securing a necessary memory capacity, it is expected that large capacity DRAMs such as 4G/16G-bit memory devices that may appear in the future may not be able to realize a short refresh cycle of the currently available level. More specifically, since DRAMs are adapted to store data in terms of stored electric charge Q(Q=C.times.V where C is the capacitance of the capacitor and V is the voltage applied to the capacitor), the capacitor area is inevitably reduced to make it difficult to secure the stored electric charge required for the capacitors to operate as the device is micronized. Therefore, there is a strong demand for a new memory device/new material that can secure a requisite volume of information (that correspond to a requisite stored electric charge of a known device of the above described type) without requiring complex manufacturing steps if remarkably downsized.
In an attempt to meet the demand, there have been proposed a DRAM where film of a material with a high dielectric constant such as Ba.sub.x Sr.sub.1-x TiO.sub.3 (0.1&lt;x&lt;0.9) is used for capacitor s in place of conventional silicon oxide film (dielectric constant=3.9) or silicon nitride film (dielectric constant=7.8) (IEDM, 95 Technical Digest, pp.115-117, "Novel Stacked Capacitor Technology for 1 Gbit DRAMs with CVD-(Ba, Sr) TiO.sub.3 Thin Films on a Thick Storage Node of Ru") and a FeRAM (ferroelectric memory) making using of the hysteresis characteristics of a ferroelectric material as shown in FIG. 1.
However, a highly dielectric material will inevitably show a significant reduction in the dielectric constant if it is used to form thin film (with a thickness between 10 and 50 nm) so that a DRAM with a large memory capacity of 1 to 4 Gbits will have to be designed to show a three-dimensional configuration, making it difficult to reduce the number of manufacturing steps and the manufacturing cost. For example, a material that shows a dielectric constant exceeding 1,000 when it takes the form of a film with a thickness of 200 nm will lose its dielectric constant to a level of about 200 when it is made into a thin film with a thickness between 10 and 20 nm that can feasibly be used for memory devices of the 0.1 .mu.m generation.
As for FeRAMs, on the other hand, ferroelectric substances such as Pb(Zr, Ti)O.sub.3 and SrBi.sub.2 Ta.sub.2 O.sub.9 that have been studied extensively show a remarkable reduction in the residual dielectric polarization when they are made into a thin film that can feasibly be used for integrated circuits so that the level of polarization satisfactory for memory devices of the 0.1 .mu.m generation to operate to store enough data will not be obtained.
The use of monocrystalline (Ba, Sr)TiO.sub.3 film has been proposed recently as a solution to the above identified problems (see Kazuhide ABE et al. Japanese Patent Application Laid-Open No. 08-139292). A film of monocrystalline (Ba, Sr) TiO.sub.3 can be made to show properties both as a high dielectric film and a ferroelectric film by selecting appropriate values for the Ba and Sr contents. If it is made to have a composition good for a highly dielectric film (e.g., B.sub.0.5 Sr.sub.0.5 TiO.sub.3), a thin film of the substance will show a very high dielectric constant when it has a thickness of 10 nm.
If, on the other hand, it is made to have a composition of B.sub.0.3 Sr.sub.0.7 TiO.sub.3, the film shows properties as a highly ferroelectric substance. Unlike Pb(Zr, Ti)O.sub.3 or (Ba, Sr) TiO.sub.3 pointed out above, this substance does not lose its ferroelectricity if it is made into a thin film with a thickness of about 10 nm and hence seems promising for FeRAMs of the 0.1 .mu.m generation. In short, it may be possible to prepare DRAMs and FeRAMs from this substance by appropriately modifying the Ba and Sr contents.
However, since the properties of the substance as a highly dielectric substance and as a ferroelectric substance become apparent only the substance takes the form of a monocrystalline thin film, a monocrystalline thin film of the substance has to be produced on an Si substrate by epitaxial growth if it is to be used for an integrated circuit. There has been proposed a technique of sequentially forming an electroconductive oxide film having a crystal structure same as that of BST and a BST film by epitaxial growth with a buffer layer arranged on the Si substrate in order to alleviate the difference in the lattice constant.
It should be noted, however, that capacitors cannot be produced with ease on a DRAM or FeRAM by epitaxially growing a film of the substance because there are transistors already formed on the DRAM or FeRAM. This is because an insulator film is normally stacked on the transistors, whereas epitaxial growth requires information of the bearing of the crystals of the Si substrate.
FIG. 2 of the accompanying drawing shows a schematic cross sectional view of a known semiconductor memory device having a COB (capacitor over bit line) structure.
Such a device is prepared by firstly forming an element isolating region 2 and a diffusion layer 5 in an Si substrate 1 and then a gate electrode 3 and a bit line 6 are formed sequentially on the substrate before a contact hole is cut through the interlevel dielectric layers 4 and 7 filled into the interlayer gaps. Then, a monocrystalline Si layer 8 is formed to fill the contact hole by means of an Si epitaxial growth technique and lower electrode layers 9 and 10 are formed thereon. The surface of the device is polished typically by CMP (chemical mechanical polishing). Finally, a capacitor insulator film 11 which is typically a (Ba, Sr) TiO.sub.3 film and an upper electrode layer 12 are formed thereon.
Since the contact hole is normally designed according to a minimal design rule, it shows an opening not square but circular. It is extremely difficult to selectively deposit Si film by epitaxial growth in such a round and deep contact hole and, if deposited successfully, such an epitaxially grown crystalline film may safely be assumed to contain a number of flaws in it.
Meanwhile, when polishing the interlevel dielectric film 7 and the electrode layer 10 to realize a smooth surface by CMP, steps may be formed at the edges of the electrode layer 10 because it is difficult to polish them at a same rate. Such steps adversely affect the effort of obtaining a capacitor insulator film 11 with a uniform film thickness and the produced uneven insulator film 11 will gradually lose its reliability.
In other words, in order to realize a capacitor insulator film that is a monocrystalline film of a highly dielectric substance or a ferroelectric substance, there need to be an underlying electrode layer that is oriented in the direction of (100) and highly smooth. However, it is extremely difficult to form a storage node with epitaxial Si on a gate electrode and a bit line and then produce a (100)-oriented electrode layer thereon in a self-aligning manner. It is also difficult to produce a flat and smooth lower electrode structure.
Thus, while DRAMs and FeRAMs using monocrystalline BST film for the capacitor insulator film have been proposed as novel memory devices that can securely store a sufficient amount of data if micronized, the process of manufacturing such DRAMs or FeRAMs involves complex steps for producing fine capacitor structures.
Additionally, it is highly difficult to form a monocrystalline underlying electrode layer on a gate electrode and a bit line for a layer of a ferroelectric or highly dielectric substance such as (Ba, Sr) TiO.sub.3 to be formed by epitaxial growth without degrading the performance of the capacitor dielectric film to be formed thereon.